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ltm4606 1 4606fb typical a pplica t ion fea t ures descrip t ion ultralow emi 28v in , 6a dc/dc module regulator the ltm ? 4606 is a complete en55022 class b certified noise high voltage 6a switching mode dc/dc power supply. included in the package are the switching controller, power fets, inductor, and all support components. the on-board input filter and noise cancellation circuits achieve low noise operation, thus effectively reducing the electromagnetic interference (emi). operating over an input voltage range of 4.5v to 28v, the ltm4606 supports an output voltage range of 0.6v to 5v, set by a single resistor. this high ef - ficiency design delivers 6a continuous current (8a peak). only bulk input and output capacitors are needed to finish the design. high switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. the device supports output voltage tracking and output volt- age margining. furthermore, the module ? regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows polyphase ? operation for high load currents. the ltm4606 is offered in a space saving and thermally enhanced 15mm 15mm 2.8mm lga package, which enables utilization of unused space on the bottom of pc boards for high density point of load regulation. the ltm4606 is pb-free and rohs compliant. a pplica t ions n complete low emi switch mode power supply n wide input voltage range: 4.5v to 28v n 6a dc typical, 8a peak output current n 0.6v to 5v output voltage range n en55022 class b certified n output voltage tracking and margining n pll frequency synchronization n 1.75% total dc error n power good output n current foldback protection (disabled at start-up) n parallel/current sharing n ultrafast transient response n current mode control n up to 93% efficiency at 5v in , 3.3v out n programmable soft-start n output overvoltage protection n C55c to 125c operating temperature range (l tm4606mpv) n small surface mount footprint, low profile package (15mm 15mm 2.8mm) n asics or fpga transceivers n telecom, servers and networking equipment n industrial equipment n rf equipment l , lt, ltc, ltm, linear technology, the linear logo, module and polyphase are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ultralow noise 2.5v/6a power supply with 4.5v to 28v input radiated emission scan at 12v in , 2.5v out /6a pgood run comp intv cc drv cc f set track/ss v d fcb marg0 marg1 mpgm v out v fb v in track/ss control 47pf c out 2.5v at 6a c in 10f 35v ceramic x2 4.5v to 28v pllin clock sync on/off ltm4606 sgnd pgnd margin control r fb 19.1k 392k 5% margin 4606 ta01a 10f 35v frequency (mhz) 30 128.1 226.2 324.3 520.5 422.4 618.6 716.7 814.8 912.9 1010 4606 ta01b signal amplitude (dbv/m) 50 40 30 20 10 0 ?10 ?20 ?30
ltm4606 2 4606fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) drv cc , v out ................................................ C0 .3v to 6v pllin, fcb, track/ss, mpgm, marg0, marg1, pgood, run .............. C 0.3v to intv cc + 0.3v v fb , comp ................................................ C0 .3v to 2.7v v in , v d ....................................................... C0 .3v to 28v internal operating temperature range (note 2) e and i g rades ................................... C 40c to 125c mp grade ........................................... C 55c to 125c junction temperature ........................................... 1 25c storage temperature range .................. C 45c to 125c lga package 133-lead (15mm 15mm 2.8mm) top view marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc track/ss sgnd 12 2 1 4 3 5 6 9 8 10 11 7 lkjhgfedcb m a t jmax = 125c, ja = 15c/w, jcbottom = 6c/w, jctop = 16c/w ja derived from 95mm 76mm pcb with 4 layers weight = 1.7g or d er in f or m a t ion lead free finish tray part marking* package description temperature range ltm4606ev#pbf ltm4606ev#pbf ltm4606v 133-lead (15mm 15mm 2.8mm) lga C40c to 125c ltm4606iv#pbf ltm4606iv#pbf ltm4606v 133-lead (15mm 15mm 2.8mm) lga C40c to 125c ltm4606mpv#pbf ltm4606mpv#pbf ltm4606mpv 133-lead (15mm 15mm 2.8mm) lga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ symbol parameter conditions min typ max units v in(dc) input dc voltage l 4.5 28 v v out(dc) output voltage, total variation with line and load c in = 10f x2, c out = 200f; fcb = 0 v in = 5v to 28v, i out = 0a to 6a, (note 4) l 1.474 1.5 1.526 v input specifications v in(uvlo) undervoltage lockout threshold i out = 0a 3.2 4 v i inrush(vin) input inrush current at start-up i out = 0a, c in = 10f x2, c out = 200f, v out = 1.5v v in = 5v v in = 12v 0.6 0.7 a a the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. per typical application (front page) configuration, r fb = 40.2k. e lec t rical c harac t eris t ics
ltm4606 3 4606fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. per typical application (front page) configuration, r fb = 40.2k. symbol parameter conditions min typ max units i q(vin) input supply bias current v in = 5v, v out = 1.5v, switching continuous v in = 12v, v out = 1.5v, switching continuous shutdown, run = 0, v in = 12v 27 25 22 ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 6a v in = 5v, v out = 1.5v, i out = 6a 0.96 2.18 a a intv cc v in = 12v, run > 2v no load 4.7 5 5.3 v output specifications i out(dc) output continuous current range v in = 12v, v out = 1.5v (note 4) 0 6 a dv out(line) / v out line regulation accuracy v out = 1.5v, fcb = 0v, v in = 4.5v to 28v, i out = 0a l 0.05 0.3 % dv out(load)/ v out load regulation accuracy v out = 1.5v, fcb = 0v, i out = 0a to 6a v in = 12v (note 4) l 0.3 % v in(ac) input ripple voltage i out = 0a, c in = 10f x5r ceramic x3 and 100f electrolytic v in = 5v, v out = 1.5v v in = 12v, v out = 1.5v 2 3 mv p-p mv p-p v out(ac) output ripple voltage i out = 0a, c out = 22f x5r ceramic x3 and 100f x5r ceramic v in = 5v, v out = 1.5v v in = 12v, v out = 1.5v 8 11 mv p-p mv p-p f s output ripple voltage frequency i out = 5a, v in = 12v, v out = 1.5v 900 khz dv out(start) turn-on overshoot, track/ss = 10nf c out = 200f, v out = 1.5v, i out = 0a v in = 12v v in = 5v 20 20 mv mv t start turn-on time, track/ss = open c out = 200f; v out = 1.5v, i out = 1a resistive load v in = 5v v in = 12v 0.5 0.5 ms ms dv out(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 22f ceramic, 470f x2 v in = 12v v out = 1.5v 35 mv t settle settling time for dynamic load step v in = 12v load: 0% to 50% to 0% of full load, v in = 12v 25 s i out(pk) output current limit c out = 200f v in = 5v, v out = 1.5v v in = 12v, v out = 1.5v 10 10 a a control section v fb voltage at v fb pin i out = 0a, v out = 1.5v l 0.591 0.6 0.609 v v run run pin on/off threshold 1 1.5 1.9 v i ss / track soft-start charging current v ss / track = 0v C1 C1.5 C2 a v fcb forced continuous threshold 0.57 0.6 0.63 v i fcb forced continuous pin current v fcb = 0v C1 C2 a t on(min) minimum on time (note 3) 50 100 ns t off(min) minimum off time (note 3) 250 400 ns r pllin pllin input resistor 50 kw
ltm4606 4 4606fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. per typical application (front page) configuration, r fb = 40.2k. symbol parameter conditions min typ max units i drvcc current into drv cc pin v out = 1.5v, i out = 1a 15 25 ma r fbhi resistor between v out and v fb pins 60.098 60.4 60.702 k w run max volts from run to gnd maximum 5.1v zener clamp 5 v margin section mpgm margin reference voltage sets a current 1.18 v marg0, marg1 voltage thresholds 1.4 v pgood dv fbh pgood upper threshold v fb rising 7 10 13 % dv fbl pgood lower threshold v fb falling C7 C10 C13 % dv fb(hys) pgood hysteresis v fb returning 1.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4606e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4606i is guaranteed to meet specifications over the C40c to 125c internal operating temperature range. the ltm4606mp is guaranteed and tested over the C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: 100% tested at die level only. note 4: see output current derating curves for different v in , v out and t a .
ltm4606 5 4606fb typical p er f or m ance c harac t eris t ics efficiency vs load current with 5v in (fcb = 0) efficiency vs load current with 12v in (fcb = 0) efficiency vs load current with 24v in (fcb = 0) 1.2v transient response 1.5v transient response 1.8v transient response 2.5v transient response 3.3v transient response C55c, start-up, i out = 0a load current (a) 0 efficiency (%) 100 90 70 80 60 50 4606 g01 654321 0.6v out 1.2v out 1.8v out 2.5v out 3.3v out load current (a) 0 efficiency (%) 100 90 70 80 60 50 4606 g02 654321 1.2v out 1.5v out 2.5v out 3.3v out 5v out load current (a) 0 efficiency (%) 100 90 70 80 60 50 4606 g03 654321 2.5v out 3.3v out 5v out 4606 g04 50s/div 1.2v at 3.5a/s load step c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic i out 2a/div v out 50mv/div 4606 g05 50s/div 1.5v at 3.5a/s load step c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic i out 2a/div v out 50mv/div 4606 g06 50s/div 1.8v at 3.5a/s load step c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic i out 2a/div v out 50mv/div 4606 g07 50s/div 2.5v at 3.5a/s load step c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic i out 2a/div v out 50mv/div 4606 g08 50s/div 3.3v at 3.5a/s load step c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic i out 2a/div v out 100mv/div v out 0.5v/div i in 0.5a/div 1ms/div 4606 g09 v in = 12v v out = 1.5v c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic soft-start = 3.9nf
ltm4606 6 4606fb typical p er f or m ance c harac t eris t ics start-up, i out = 6a (resistive load) short-circuit protection, i out = 0a short-circuit protection, i out = 6a v in to v out step-down operation region input ripple output ripple start-up, i out = 0a C55c, start-up, i out = 6a v fb vs temperature v out 0.5v/div i in 0.5a/div 1ms/div 4606 g10 v in = 12v v out = 1.5v c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic soft-start = 3.9nf v out 0.5v/div i in 0.5a/div 1ms/div 4606 g11 v in = 12v v out = 1.5v c out = 1 22f, 6.3v ceramic 1 330f, 4v sanyo poscap soft-start = 3.9nf v out 0.5v/div i in 0.5a/div 1ms/div 4606 g12 v in = 12v v out = 1.5v c out = 1 22f, 6.3v ceramic 1 330f, 4v sanyo poscap soft-start = 3.9nf v out 2v/div i in 0.2a/div 50s/div 4606 g13 v in = 12v v out = 2.5v c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic soft-start = 0.1f v out 1v/div i in 2a/div 50s/div 4606 g14 v in = 12v v out = 2.5v c out = 2 22f, 10v ceramic 1 100f, 6.3v ceramic soft-start = 0.1f v out (v) 0.6 v in (v) 28 24 8 20 16 12 4.5 2.5 4.5 1.5 3.5 4606 g15 5.0 2.0 4.0 1.0 3.0 see frequency adjustment section for operations outside this region operation region with default frequency temperature (c) ?55 0.594 0.596 0.598 v fb (v) 5?25 4606 g16 0.606 0.604 0.602 0.600 125956535 v in 10mv/div 2s/div 4606 g17 v in = 5v v out = 1v at 6a c in = 3 10f, 25v ceramic 1 150f bulk bw = 300mhz v out 2mv/div 2s/div 4606 g18 v in = 5v v out = 1v at 6a c out = 2 22f, 6.3v ceramic 1 100f, 6.3v ceramic bw = 300mhz
ltm4606 7 4606fb p in func t ions v in (bank 1): power input pins. apply input voltage be- tween these pins and pgnd pins. recommend placing input decoupling capacitance directly between v in pins and pgnd pins. v out (bank 3): power output pins. apply output load between these pins and pgnd pins. recommend placing output decoupling capacitance directly between these pins and pgnd pins (see figure below). pgnd (bank 2): power ground pins for both input and output returns. v d (pins b7, c7): top fet drain pins. add more capacitors between v d and ground to handle the input rms current and reduce the input ripple further. drv cc (pins c10, e11, e12): these pins normally con- nect to intv cc for powering the internal mosfet drivers. they can be biased up to 6v from an external supply with about 50ma capability, or an external circuit as shown in figure 18. this improves efficiency at the higher input voltages by reducing power dissipation in the modules. intv cc (pin a7): this pin is for additional decoupling of the 5v internal regulator. pllin (pin a8): external clock synchronization input to the phase detector. this pin is internally terminated to sgnd with a 50k resistor. apply a clock with high level above 2v and below intv cc . see the applications infor - mation section. fcb (pin m12): forced continuous input. connect this pin to sgnd to force continuous synchronization operation at low load, to intv cc to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. track/ss (pin a9): output voltage tracking and soft-start pin. when the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. a soft-start capacitor can be used for soft-start turn-on as a standalone regulator. slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. see the applications information section. mpgm (pins a12, b11): programmable margining input. a resistor from these pins to ground sets a current that is equal to 1.18v/r. this current multiplied by 10k w will equal a value in millivolts that is a percentage of the 0.6v reference voltage. see the applications information section. to parallel ltm4606s, each requires an individual mpgm resistor. do not tie mpgm pins together. f set (pin b12): frequency set internally to 800khz in continuous conducting mode at light load. an external resistor can be placed from this pin to ground to increase frequency. this pin can be decoupled with a 1000pf capacitor. see the applications information section for frequency adjustment. v fb (pin f12): the negative input of the error amplifier. internally, this pin is connected to v out with a 60.4k preci- sion resistor. different output voltages can be programmed with an additional resistor between the v fb and sgnd pins. see the applications information section. marg0 (pin c12): lsb logic input for the margining function. together with the marg1 pin, the marg0 pin will determine if a margin high, margin low, or no margin state is applied. the pin has an internal pulldown resistor of 50k. see the applications information section. marg1 (pins c11, d12): msb logic input for the margin- ing function. together with the marg0 pin, the marg1 pins will determine if a margin high, margin low, or no margin state is applied. the pins have an internal pull-down resistor of 50k. see the applications information section. sgnd (pins d9, h12): signal ground pins. these pins connect to pgnd at output capacitor point. comp (pins a11, d11): current control threshold and error amplifier compensation point. the current com- parator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.7v corresponding to zero sense voltage (zero current). pgood (pin g12): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires.
ltm4606 8 4606fb run (pins a10, b9): run control pins. a voltage above 1.9v will turn on the module, and below 1v will turn off the module. a programmable uvlo function can be ac- complished with a resistor from v in to this pin that has a 5.1v zener to ground. maximum pin voltage is 5v. p in func t ions nc (pins j12, k12, l12): these pads must be left floating (electrical open circuit) and are used for increased solder integrity strength. marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc track/ss sgnd 12 2 1 4 3 5 6 9 8 10 11 7 lkjhgfedcb m a
ltm4606 9 4606fb b lock diagra m d ecoupling require m en t s symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.5v to 28v, v out = 2.5v) i out = 6a 10 f c out external output capacitor requirement (v in = 4.5v to 28v, v out = 2.5v) i out = 6a 100 200 f t a = 25c. use figure 1 configuration. figure 1. simplified block diagram + internal comp sgnd comp pgood run >1.9v = on <1v = off max = 5v marg1 marg0 mpgm fcb pllin c ss intv cc drv cc track/ss v fb f set 50k 41.2k r fb 19.1k 50k 60.4k v out 5.1v zener power control m1 v in 4.5v to 28v v d v out 2.5v at 6a m2 50k 22f 1h 1.5f c in + c out pgnd 4606 f01 c d 10k 4.7f input filter noise cancel- lation
ltm4606 10 4606fb o pera t ion power module description the ltm4606 is a standalone non-isolated switching mode dc/dc power supply. it can deliver up to 6a of dc output current with some external input and output capacitors. this module provides precisely regulated output voltage programmable via one external resistor from 0.6v dc to 5.0v dc over a 4.5v to 28v input voltage range. the typical application schematic is shown in figure 20. the ltm4606 has an integrated constant on-time current mode regulator, ultralow r ds(on) fets with fast switch - ing speed and integrated schottky diodes. with current mode control and internal feedback loop compensation, the ltm4606 module has sufficient stability margins and good transient performance under a wide range of operat - ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limiting. besides, foldback current limiting is provided in an overcurrent condition while v fb drops. internal over - voltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, internal top fet m1 is turned off and bottom fet m2 is turned on and held on until the overvoltage condition clears. input filter and noise cancellation circuits reduce the noise coupling to i/o sides, and ensure the electromagnetic interference (emi) to meet en55022 class b limits. pulling the run pin below 1v forces the controller into its shutdown state, turning off both m1 and m2. at low load currents, discontinuous mode (dcm) operation can be enabled to achieve higher efficiency compared to continu- ous mode (ccm) by setting the fcb pin higher than 0.6v. when the drv cc pin is connected to intv cc an integrated 5v linear regulator powers the internal gate drivers. if a 5v external bias supply is applied on the drv cc pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. this is especially true at the higher input voltage range. the mpgm, marg0 and marg1 pins are used to sup- port voltage margining, where the percentage of margin is programmed by the mpgm pin, and the marg0 and marg1 selected margining. the pllin pin provides fre- quency synchronization of the device to an external clock. the track/ss pin is used for power supply tracking and soft-start programming.
ltm4606 11 4606fb the typical ltm4606 application circuit is shown in fig - ure 20. external component selection is primarily deter - mined by the maximum load current and output voltage. refer to table 2 for specific external capacitor requirements for a particular application. v in to v out step-down ratios under the default frequency, there are restrictions in the maximum v in and v out step-down ratio that can be achieved for a given input voltage. these constraints are caused by the limitation of the minimum on and off time in the internal switches. refer to the frequency adjustment section to change the switching frequency and get wider input and output ranges. see the thermal considerations and output current derating section in this data sheet for the current restrictions. output voltage programming and margining the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor connects the v out and v fb pins together. adding a resistor r fb from the v fb pin to the sgnd pin programs the output voltage: v out = 0.6v 60.4k + r fb r fb table 1. r fb standard 1% resistor values vs v out r fb (k) open 60.4 40.2 30.1 25.5 19.1 13.3 8.25 v out (v) 0.6 1.2 1.5 1.8 2 2.5 3.3 5 the mpgm pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6v reference offset for margining. a 1.18v reference divided by the a pplica t ions i n f or m a t ion rpgm resistor on the mpgm pin programs the current. calculate v out(margin) : v out(margin) = %v out 100 ? v out where %v out is the percentage of v out you want to margin, and v out(margin) is the margin quantity in volts: r pgm = v out 0.6v ? 1.18v v out(margin) ? 10k where rpgm is the resistor value to place on the mpgm pin to ground. the output margining will be margining of the value. this is controlled by the marg0 and marg1 pins. see the truth table below: marg1 marg0 mode low low no margin low high margin up high low margin down high high no margin input capacitors and input emi noise attenuation the ltm4606 is designed to achieve low input conducted emi noise due to the fast switching of turn-on and turn-off. in the ltm4606, a high frequency inductor is integrated to the input line for noise attenuation. v d and v in pins are available for external input capacitors to form a high frequency filter. as shown in figure 19, the ceramic capacitor c1 on the v d pins is used to handle most of the rms current into the converter, so careful attention is needed for capacitor c1 selection. for a buck converter, the switching duty cycle can be estimated as: d = v out v in
ltm4606 12 4606fb without considering the inductor ripple current, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) ? d ? 1C d ( ) in the above equation, is the estimated efficiency of the power module. note the capacitor ripple current ratings are often based on temperature and hours of life. this makes it advisable to properly derate the capacitor, or choose a capacitor rated at a higher temperature than required. always contact the capacitor manufacturer for derating requirements. in a typical 6a output application, one or two very low esr x5r or x7r, 10f ceramic capacitors are recom- mended for c1. this decoupling capacitor should be placed directly adjacent to the module v d pins in the pcb layout to minimize the trace inductance and high frequency ac noise. each 10f ceramic is typically good for 2 to 3 amps of rms ripple current. refer to your ceramics capacitor catalog for the rms current ratings. to attenuate high frequency noise, extra input capacitors should be connected to the v in pads and placed before the high frequency inductor to form the filter. one of these low esr ceramic capacitors is recommended to be placed close to the connection into the system board. a large bulk 100f capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. figure 2 shows the radiated emi test results to a pplica t ions i n f or m a t ion meet en55022 class b. for different applications, input capacitance may be varied to meet different radiated emi limits. output capacitors the ltm4606 is designed for low output voltage ripple. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient requirements. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical capacitance is 200f if all ceramic output capacitors are used. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3a/s transient. the table optimizes total equivalent esr and total bulk capacitance to maximize transient performance. multiphase operation with multiple ltm4606 devices in parallel will lower the effective output ripple current due to the phase interleaving operation. refer to figure 3 for the normalized output ripple current versus the duty cycle. figure 3 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. for example, each phases inductor ripple current dir at zero duty cycle is ~2.5a for a 12v to 2.5v design. the duty cycle is about 0.21. the 2-phase curve has a ratio of ~0.58 for a duty cycle of 0.21. this 0.58 ratio of output ripple current to the inductor ripple current dir at 2.5a equals ~1.5a of the output ripple current (?i l ). the output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. the equation is: d v out(p ? p) d i l 8 ? f ? n ? c out ? ? ? ? ? ? + esr ? d i l where f is the frequency and n is the number of paralleled phases. frequency (mhz) 30 128.1 226.2 324.3 520.5 422.4 618.6 716.7 814.8 912.9 1010 4606 f02 signal amplitude (dbv/m) 50 40 30 20 10 0 ?10 ?20 ?30 figure 2. radiated emission scan with 12v in to 2.5v out at 6a (1100f x7r ceramic c out )
ltm4606 13 4606fb a pplica t ions i n f or m a t ion fault conditions: current limit and overcurrent foldback ltm4606 has a current mode controller, which inher - ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. to further limit current in the event of an overload condi - tion, the ltm4606 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. soft-start and tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a capacitor on this pin will program the ramp rate of the output voltage. a 1.5a current source will charge up the external soft-start capacitor to 80% of the 0.6v internal voltage reference plus or minus any margin delta. this will control the ramp of the internal reference and the output voltage. the total soft-start time can be calculated as: t softstart ? 0.8 ? 0.6v v out(margin) ( ) ? c ss 1.5a when the run pin falls below 2.5v, then the ss pin is reset to allow for proper soft-start control when the regulator is enabled again. current foldback and force continuous mode are disabled during the soft-start process. the soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. duty cycle (v o /v in ) 0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4612 f05 6-phase 4-phase 3-phase 2-phase 1-phase peak-to-peak output ripple current dir ratio = figure 3. normalized output ripple current vs duty cycle, dlr = v o t/l i
ltm4606 14 4606fb output voltage tracking output voltage tracking can be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 4 shows an example of coincident tracking where the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider. ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. the master output must be greater than the slave output for the tracking to work. figure 5 shows the coincident output tracking characteristics. run enable the run pin is used to enable the power module. the pin has an internal 5.1v zener to ground. the pin can be driven with a logic input not to exceed 5v. the run pin can also be used as an undervoltage lock out (uvlo) function by connecting a resistor divider from the input supply to the run pin: v uvlo = r1 + r2 r2 ? 1.5v where r2 is the bottom resistor of the divider, r1 is the top resistor of the divider. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point and tracks with margining. comp pin this pin is the external compensation pin. the module has already been internally compensated for most output voltages. table 2 is provided for most application require - ments. ltpowercad? is available for other control loop optimization. fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when in- ductor current reverses. fcb pin below the 0.6v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintain low output ripple. a pplica t ions i n f or m a t ion pgood v d run comp intv cc drv cc track/ss f set v out v fb fcb marg0 marg1 mpgm track control pllin ltm4606 19.1k 100k r1 19.1k master output r2 60.4k c out slave output 2.5v 4606 f04 c in v in pgnd sgnd v in figure 4. output voltage coincident tracking figure 5. coincident tracking characteristics output voltage time 4606 f05 master output slave output
ltm4606 15 4606fb a pplica t ions i n f or m a t ion pllin the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the frequency range is 30% around the operating frequency. a pulse detection circuit is used to detect a clock on the pllin pin to turn on the phase lock loop. the pulse width of the clock has to be at least 400ns and 2v in amplitude. during the start-up of the regulator, the phase-lock loop function is disabled. intv cc and drv cc connection an internal low dropout regulator produces an internal 5v supply that powers the control circuitry and drv cc for driving the internal power mosfets. therefore, if the system does not have a 5v power rail, the ltm4606 can be directly powered by vin. the gate driver current through the ldo is about 20ma. the internal ldo power dissipation can be calculated as: p ldo_loss = 20ma ? (v in C 5v) the ltm4606 also provides an external gate driver voltage pin drv cc . if there is a 5v rail in the system, it is recom- mended to connect drv cc pin to the external 5v rail. this is especially true for higher input voltages. do not apply more than 6v to the drv cc pin. a 5v output can be used to power the drv cc pin with an external circuit as shown in figure 18. parallel operation of the module the ltm4606 device is an inherently current mode con - trolled device. parallel modules will have very good current sharing. this will balance the thermals on the design. the voltage feedback equation changes with the variable n as modules are paralleled: v out = 0.6v 60.4k n + r fb r fb n is the number of paralleled modules. thermal considerations and output current derating in different applications, ltm4606 operates in a variety of thermal environments. the maximum output current is limited by the environment thermal condition. sufficient cooling should be provided to help ensure reliable opera- tion. when the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. the power loss curves in figures 6 and 7 can be used in coordination with the load current derating curves in figures 8 to 15 for calculating an approximate ja for the module. the graphs delineate between no heat sink, and a bga heat sink. each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junc- tion temperature of the power module at 125c maximum. each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate ja of the condition. each figure has three curves that are taken at three different air flow conditions. tables 3 and 4 provide the approximate ja for figures 8 to 15. a complete explanation of the thermal characteristics is provided in the thermal application note an110. safety considerations the ltm4606 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. radiated emi noise high radiated emi noise is a disadvantage for switching regulators by nature. fast switching turn-on and turn-off make large di/dt change in the converters, which act as the radiation sources in most systems. the ltm4606 integrates the feature to minimize the radiated emi noise for applications with low noise requirements. optimized gate driver for the mosfet and noise cancellation network are installed inside the ltm4606 to achieve low radiated emi noise. figure 16 shows a typical example for ltm4606 to meet the class b of en55022 radiated emission limit.
ltm4606 16 4606fb a pplica t ions i n f or m a t ion figure 6. 1.5v power loss figure 7. 3.3v power loss figure 8. no heat sink figure 9. bga heat sink figure 10. no heat sink figure 11. bga heat sink output current (a) 0 2.0 2.5 3 5 4606 f06 1.5 1.0 1 2 4 6 7 0.5 0 power loss (w) 12v loss 5v loss output current (a) 0 2.0 2.5 4.0 3.5 3 5 4606 f07 1.5 1.0 1 2 4 6 7 0.5 0 3.0 power loss (w) 24v loss 12v loss ambient temperature (c) 75 0 maximum load current (a) 1 2 3 4 5 6 80 85 90 95 4606 f08 5v in , 1.5v out , 0lfm 5v in , 1.5v out , 200lfm 5v in , 1.5v out , 400lfm ambient temperature (c) 75 0 maximum load current (a) 1 2 3 4 5 6 80 85 90 95 4606 f09 5v in , 1.5v out , 0lfm 5v in , 1.5v out , 200lfm 5v in , 1.5v out , 400lfm ambient temperature (c) 70 0 maximum load current (a) 1 2 3 4 5 6 75 80 85 90 4606 f11 95 12v in , 1.5v out , 0lfm 12v in , 1.5v out , 200lfm 12v in , 1.5v out , 400lfm ambient temperature (c) 70 0 maximum load current (a) 1 2 3 4 5 6 75 80 85 90 4606 f10 95 12v in , 1.5v out , 0lfm 12v in , 1.5v out , 200lfm 12v in , 1.5v out , 400lfm
ltm4606 17 4606fb a pplica t ions i n f or m a t ion figure 12. no heat sink figure 13. bga heat sink figure 15. bga heat sink figure 14. no heat sink ambient temperature (c) 70 0 maximum load current (a) 1 2 3 4 5 6 75 80 85 90 4606 f12 95 12v in , 3.3v out , 0lfm 12v in , 3.3v out , 200lfm 12v in , 3.3v out , 400lfm ambient temperature (c) 70 0 maximum load current (a) 1 2 3 4 5 6 75 80 85 90 4606 f13 95 12v in , 3.3v out , 0lfm 12v in , 3.3v out , 200lfm 12v in , 3.3v out , 400lfm ambient temperature (c) 60 0 maximum load current (a) 1 2 3 4 5 6 65 70 75 80 4606 f14 85 24v in , 3.3v out , 0lfm 24v in , 3.3v out , 200lfm 24v in , 3.3v out , 400lfm ambient temperature (c) 60 0 maximum load current (a) 1 2 3 4 6 65 70 75 80 4606 g15 85 90 5 24v in , 3.3v out , 0lfm 24v in , 3.3v out , 200lfm 24v in , 3.3v out , 400lfm frequency (mhz) 30 128.1 226.2 324.3 520.5 422.4 618.6 716.7 814.8 912.9 1010 4606 f16 signal amplitude (dbv/m) 50 40 30 20 10 0 ?10 ?20 ?30 figure 16. radiated emission scan with 12v in to 2.5v out at 6a (1100f x7r ceramic c out )
ltm4606 18 4606fb table 2. output voltage response vs component matrix (refer to figure 20) typical measured values c out1 vendors part number c out2 vendors part number taiyo yuden jmk316bj226ml-t501 (22f, 6.3v) sanyo poscap 6tpe220mil (220f, 6.3v) taiyo yuden jmk325bj476mm-t (47f, 6.3v) sanyo poscap 2r5tpe330m9 (330f, 2.5v) tdk c3225x5r0j476m (47f, 6.3v) sanyo poscap 4tpe330mcl (330f, 4v) v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) c out2 (bulk) v in (v) droop (mv) peak to peak (mv) recovery time (s) load step (a/s) r fb (k w ) 1.2 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 5 34 68 30 3 60.4 1.2 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 5 22 40 26 3 60.4 1.2 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 5 20 40 24 3 60.4 1.2 2 10f 35v 150f 35v 4 47f 6.3v none 5 32 60 18 3 60.4 1.2 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 12 34 68 30 3 60.4 1.2 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 12 22 40 26 3 60.4 1.2 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 12 20 39 24 3 60.4 1.2 2 10f 35v 150f 35v 4 47f 6.3v none 12 29.5 55 18 3 60.4 1.5 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 5 35 70 30 3 40.2 1.5 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 5 25 48 30 3 40.2 1.5 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 5 24 47.5 26 3 40.2 1.5 2 10f 35v 150f 35v 4 47f 6.3v none 5 36 68 26 3 40.2 1.5 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 12 35 70 30 3 40.2 1.5 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 12 25 48 30 3 40.2 1.5 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 12 24 45 26 3 40.2 1.5 2 10f 35v 150f 35v 4 47f 6.3v none 12 32.6 61.9 26 3 40.2 1.8 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 5 38 76 37 3 30.1 1.8 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 5 29.5 57.5 30 3 30.1 1.8 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 5 28 55 26 3 30.1 1.8 2 10f 35v 150f 35v 4 47f 6.3v none 5 43 80 26 3 30.1 1.8 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 12 38 76 37 3 30.1 1.8 2 10f 35v 150f 35v 1 47f 6.3v 330f 2.5v 12 28 55 30 3 30.1 1.8 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 12 27 52 26 3 30.1 1.8 2 10f 35v 150f 35v 4 47f 6.3v none 12 36.4 70 26 3 30.1 2.5 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 5 38 78 40 3 19.1 2.5 2 10f 35v 150f 35v 1 47f 6.3v 330f 4v 5 37.6 74 34 3 19.1 2.5 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 5 39.5 78.1 28 3 19.1 2.5 2 10f 35v 150f 35v 4 47f 6.3v none 5 66 119 12 3 19.1 2.5 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 12 38 78 40 3 19.1 2.5 2 10f 35v 150f 35v 1 47f 6.3v 330f 4v 12 34.5 66.3 34 3 19.1 2.5 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 12 35.8 68.8 28 3 19.1 2.5 2 10f 35v 150f 35v 4 47f 6.3v none 12 50 98 18 3 19.1 3.3 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 7 42 86 40 3 13.3 3.3 2 10f 35v 150f 35v 1 47f 6.3v 330f 4v 7 47 89 32 3 13.3 3.3 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 7 50 94 28 3 13.3 3.3 2 10f 35v 150f 35v 4 47f 6.3v none 7 75 141 14 3 13.3 3.3 2 10f 35v 150f 35v 1 22f 6.3v 330f 4v 12 42 86 40 3 13.3 3.3 2 10f 35v 150f 35v 1 47f 6.3v 330f 4v 12 47 88 32 3 13.3 3.3 2 10f 35v 150f 35v 2 47f 6.3v 220f 6.3v 12 50 94 28 3 13.3 3.3 2 10f 35v 150f 35v 4 47f 6.3v none 12 69 131 22 3 13.3 5 2 10f 35v 150f 35v 4 47f 6.3v none 12 110 215 20 3 8.25 5 2 10f 35v 150f 35v 4 47f 6.3v none 15 110 215 20 3 8.25 5 2 10f 35v 150f 35v 4 47f 6.3v none 20 110 217 20 3 8.25 a pplica t ions i n f or m a t ion
ltm4606 19 4606fb table 3. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 8, 10 5, 12 figure 6 0 none 13.5 figures 8, 10 5, 12 figure 6 200 none 10 figures 8, 10 5, 12 figure 6 400 none 9 figures 9, 11 5, 12 figure 6 0 bga heat sink 9.5 figures 9, 11 5, 12 figure 6 200 bga heat sink 7 figures 9, 11 5, 12 figure 6 400 bga heat sink 5 a pplica t ions i n f or m a t ion table 4. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 12, 14 12, 24 figure 7 0 none 13.5 figures 12, 14 12, 24 figure 7 200 none 11 figures 12, 14 12, 24 figure 7 400 none 10 figures 13, 15 12, 24 figure 7 0 bga heat sink 10 figures 13, 15 12, 24 figure 7 200 bga heat sink 7 figures 13, 15 12, 24 figure 7 400 bga heat sink 5 heat sink manufacturer wakefield engineering part no: ltn20069 phone: 603-635-2800 layout checklist/example the high integration of ltm4606 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout con - siderations are still necessary. ? use large pcb copper areas for high current path, in - cluding v in , pgnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v d , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? use round corners for the pcb copper layer to minimize the radiated noise. ? to minimize the emi noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers on different locations. ? do not put vias directly on pads, unless they are capped. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. ? place one or more high frequency ceramic capacitors close to the connection into the system board. figure 17 gives a good example of the recommended layout. for load current below 3a, decouple the input and output grounds. use vias to connect gnd pads to the bottom layer, then connect to the right side of the module as the output gnd. signal gnd v out v in gnd c out c in c in c out 4606 f17 figure 17. recommended pcb layout
ltm4606 20 4606fb frequency adjustment the ltm4606 is designed to typically operate at 800khz across most input conditions. the f set pin is typically left open or decoupled with an optional 1000pf capacitor. the switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. the 800khz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5v to 3.3v, and produce excessive inductor ripple currents for lower duty cycle applications like 28v to 5v. example for 5v output ltm4606 minimum on-time = 100ns; t on = ((4.8 ? 10pf)/i fset ) ltm4606 minimum off-time = 400ns; t off = t C t on , where t = 1/frequency duty cycle = t on /t or v out /v in equations for setting frequency: i fset = (v in /(3 ? r fset )), where the internal r fset is 41.2k. for 28v input operation, i fset = 227a. t on = ((4.8 ? 10pf)/ i fset ), t on = 211ns. frequency = (v out /(v in ? t on )) = (5v/ (28 ? 211ns)) ~ 850khz. the inductor ripple current begins to get high at the higher input voltages due to a larger volt- age across the inductor. the current ripple is ~5a at 20% duty cycle if the integrated inductor is 1h. the inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f set to ground to increase the switching frequency. a 4a ripple current is chosen, and the total peak current is equal to 1/2 of the 4a ripple current plus the output current. for 5v output, current is limited to 5a, so the total peak current is less than 7a. this is below the 8a peak specified value. a 150k resistor is placed from f set to ground, and the parallel combination of 150k and 41.2k equates to 32.3k. the i fset calculation with 32.3k and 28v input voltage equals 289a. this equates to a t on of 166ns. this will increase the switching frequency from 850khz to ~1mhz for the 28v to 5v conversion. the minimum on time is above 100ns at 28v input. since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 8v for the 1mhz operation due to the 400ns minimum off time. equation: t on = (v out /v in ) ? (1/ frequency) equates to a 375ns on time, and a 400ns off time. figure 18 shows an operating range of 10v to 28v for 1mhz operation with a 150k resistor to ground, and an 8v to 16v operating range for f set floating. these modifications are made to provide wider input voltage ranges for the 5v output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off-time. example for 3.3v output ltm4606 minimum on-time = 100ns; t on = ((3.3 ? 10pf)/i fset ) ltm4606 minimum off-time = 400ns; t off = t C t on , where t = 1/frequency duty cycle (dc) = t on /t or v out /v in equations for setting frequency: i fset = (v in /(3 ? r fset )), for 28v input operation, i fset = 227a, t on = ((3.3 ? 10pf)/i fset ), t on = 145ns, where the internal r fset is 41.2k. frequency = (v out /(v in ? t on )) = (3.3v/(28 ? 145ns)) ~ 810khz. the minimum on-time and minimum-off time are within specification at 146ns and 1089ns. but the 4.5v minimum input for converting 3.3v output will not meet the minimum off-time specification of 400ns. t on = 905ns, frequency = 810khz, t off = 329ns. solution lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns mini- mum off-time at 4.5v input voltage. the off-time should be about 500ns with 100ns guard band. the duty cycle for (3.3v/4.5v) = ~73%. frequency = (1 C dc)/t off or (1 C 0.73)/500ns = 540khz. the switching frequency needs to be lowered to 540khz at 4.5v input. t on = dc/ frequency, or 1.35s. the f set pin voltage compliance is 1/3 of v in , and the i fset current equates to 36a with the internal 41.2k. the i fset current needs to be 24a for 540khz operation. a resistor can be placed from v out to f set to lower the effective i fset current out of the f set pin to 24a. the f set pin is 4.5v/3 =1.5v and v out = 3.3v, therefore a 150k resistor will source 12a into the f set node and lower the i fset current to 24a. this enables the 540khz operation and the 4.5v to 28v input operation for down converting to 3.3v output as shown in figure 19. the frequency will scale from 540khz to 950khz over this input range. this provides for an effective output current of 5a over the input range. a pplica t ions i n f or m a t ion
ltm4606 21 4606fb typical a pplica t ions figure 19. 3.3v at 5a design figure 18. 10v to 28v in , 5v at 5a design pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb v in v d v out r3 100k c2 100pf c1 10f c out1 22f 6.3v c out2 220f 6.3v 5v at 5a c in 10f 35v ceramic x2 10v to 28v pllin refer to table 2 for output capacitor selections on/off ltm4606 sgnd pgnd margin control r4 100k r1 392k 5% margin + 4606 ta02 track/ss control improve efficiency for 12v input r fset 150k r fb 8.25k pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb v in v out v out r3 100k c2 100pf c out1 22f 6.3v x2 c out2 220f 6.3v 3.3v at 5a c in 10f 35v ceramic x2 4.5v to 28v pllin refer to table 2 for output capacitor selections on/off ltm4606 sgnd pgnd margin control r4 100k r fset 150k r fb 13.3k r1 392k 5% margin + 4606 ta03 track/ss control v d c1 10f
ltm4606 22 4606fb typical a pplica t ions figure 21. 2-phase, parallel 2.5v at 12a design figure 20. typical 4.5v to 28v in , 2.5v at 6a design pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb v in v out r3 100k c4 0.01f c2 100pf c out1 22f 6.3v c out2 220f 6.3v 2.5v at 6a c in 10f 35v ceramic x2 4.5v to 28v pllin clock sync on/off ltm4606 sgnd pgnd margin control r4 100k r fb 19.1k r1 392k 5% margin + 4606 ta04 v d c1 10f pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm v in v out r2 100k c4 0.33f c6 220pf c out1 22f 6.3v 4606 ta05 c out2 220f 6.3v 2.5v at 12a c7 0.1f c5 100f 35v c2 10f 35v c8 10f 35v v in 4.5v to 28v ltc6908-1 2-phase oscillator pllin clock sync 0 phase clock sync 180 phase ltm4606 sgnd pgnd pgood run comp intv cc drv cc f set track/ss v in pllin ltm4606 sgnd pgnd margin control 5% margin 5% margin r4 100k r fb 9.53k r1 392k r3 100k r5 118k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c out3 22f 6.3v c out4 220f 6.3v r6 392k + + v d c3 10f v d c1 10f
ltm4606 23 4606fb typical a pplica t ions figure 22. 2-phase, 3.3v and 2.5v outputs at 6a with tracking and margining pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm v in 3.3v r2 100k c7 0.15f c6 22pf c out1 100f 6.3v 4606 ta06 c out2 220f 6.3v 3.3v at 6a c9 0.1f c5 100f 35v c2 10f 35v c8 10f 35v v in 5v to 28v ltc6908-1 2-phase oscillator pllin clock sync 0 phase clock sync 180 phase ltm4606 sgnd pgnd pgood run comp intv cc drv cc f set track/ss v in pllin ltm4606 sgnd 3.3v track pgnd margin control 5% margin r4 100k r fb1 13.3k r fb2 19.1k r1 392k r8 60.4k r9 19.1k r3 100k r7 100k 3.3v r5 118k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 22pf c out3 100f 6.3v c out4 220f 6.3v 2.5v at 6a margin control r6 392k + + v d c3 10f v d c4 10f
ltm4606 24 4606fb typical a pplica t ions figure 23. 2-phase, 1.8v and 1.5v outputs at 6a with tracking and margining pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm v in 1.8v r2 100k c7 0.15f c6 100pf c out1 100f 6.3v 4606 ta07 c out2 220f 6.3v 1.8v at 6a c9 0.1f c5 100f 35v c2 10f 35v c8 10f 35v 4.5v to 28v ltc6908-1 2-phase oscillator pllin clock sync 0 phase clock sync 180 phase sgnd pgnd pgood run comp intv cc drv cc f set track/ss v in pllin sgnd 1.8v track pgnd margin control r4 100k r fb1 30.1k r1 392k r8 60.4k r9 40.2k r3 100k r7 100k 1.8v r5 182k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 100pf c out3 22f 6.3v c out4 220f 6.3v 1.5v at 6a margin control r fb2 40.2k r6 392k + + ltm4606 ltm4606 5% margin v d c3 10f v d c4 10f
ltm4606 25 4606fb p ackage descrip t ion pin name a1 a2 a3 a4 a5 a6 v in v in v in v in v in v in b1 b2 b3 b4 b5 b6 v in v in v in v in v in v in c1 c2 c3 c4 c5 c6 v in v in v in v in v in v in pin assignment tables (arranged by pin function) pin name d1 d2 d3 d4 d5 d6 pgnd pgnd pgnd pgnd pgnd pgnd e1 e2 e3 e4 e5 e6 e7 e8 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd f1 f2 f3 f4 f5 f6 f7 f8 f9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pin name j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 v out v out v out v out v out v out v out v out v out v out v out k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 v out v out v out v out v out v out v out v out v out v out v out l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 v out v out v out v out v out v out v out v out v out v out v out m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 v out v out v out v out v out v out v out v out v out v out v out pin name a7 a8 a9 a10 a11 a12 intv cc pllin track/ss run comp mpgm b7 b8 b9 b10 b11 b12 v d - run - mpgm f set c7 c8 c9 c10 c11 c12 v d - - drv cc marg1 marg0 d7 d8 d9 d10 d11 d12 - - sgnd - comp marg1 e9 e10 e11 e12 - - drv cc drv cc f10 f11 f12 - - v fb g12 pgood h12 sgnd j12 nc k12 nc l12 nc m12 fcb
ltm4606 26 4606fb p ackage descrip t ion lga package 133-lead (15mm 15mm 2.82mm) (reference ltc dwg # 05-08-1766 rev ?) l k j h g f e d c b m a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 133 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.10 0.10 0.05 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 13.97 bsc 1.27 bsc 13.97 bsc 0.12 ? 0.28 package bottom view c(0.30) pad 1 3 pads see notes 1 2 3 4 5 6 7 8 10 9 11 12 detail a 0.630 0.025 sq. 133x s yxeee suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 lga 133 1107 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1?
ltm4606 27 4606fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 3/10 change to features. change to absolute maximum ratings. changes to electrical characteristics. changes to related parts. 1 2 2, 3 25 b 3/11 text updated throughout the data sheet. graph replaced on the front page, figure 2, and figure 16. added value of 1h to inductor on figure 1. updated related parts. 1-28 1, 12, 17 9 28
ltm4606 28 4606fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0311 rev b ? printed in usa r ela t e d p ar t s p ackage p ho t ograph part number description comments ltm4601/ ltm4601a 12a dc/dc module regulator with pll, output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4601-1/ltm4601a-1 version has no remote sensing, lga package ltm4618 6a dc/dc module regulator with pll, output tracking 4.5v v in 26.5v, 0.8v v out 5v, synchronizable, 9mm 15mm 4.3mm lga package ltm4604a low v in 4a dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm 15mm 2.3mm lga package ltm4608a low v in 8a dc/dc module regulator 2.375v v in 5.5v, 0.6v v out 5v, 9mm 15mm 2.8mm lga package ltm4612 low noise 5a, 15v out dc/dc module regulator low noise, with pll, output tracking and margining, ltm4606 pin-compatible ltm4627 15a dc/dc module regulator 4.5v v in 20v, 0.6v v out 5v, 1.5% total dc output accuracy, 15mm 15mm 4.32mm lga package en55022 class b certified dc/dc module regulators LTM8020 high v in 0.2a dc/dc step-down module regulator 4v v in 36v, 1.25v v out 5v, 6.25mm 6.25mm 2.3mm lga package ltm8021 high v in 0.5a dc/dc step-down module regulator 3v v in 36v, 0.8v v out 5v, 6.25mm 11.25mm 2.8mm lga package ltm8022/ ltm8023 36v in , 1a and 2a dc/dc module regulators pin compatible, 4.5v v in 36v, 9mm 11.25mm 2.8mm lga package ltm8031/ ltm8032 1a, 2a emc dc/dc module regulators en55022 class b compliant, 3.6v v in 36v, 0.8v v out 10v, pin compatible, 9mm 15mm 2.82mm lga package ltm8033 3a emc dc/dc module regulator 3.6v v in 36v, 0.8v v out 24v, 11.25mm 15mm 4.32mm lga package

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